With the continuing and increasing demand for electronic devices of all kinds, there is a concurrent need to improve the quality and reduce the manufacturing time of these devices. In general, all electronic devices include at least one integrated circuit ("IC") or "chip" which integrates millions of transistors and connections on one tiny substrate of semiconductor material. The miniaturization of integrated circuits, and the products which they control, continues to be of major significance in the marketplace and a driving force to the manufacturers of such products.
In designing integrated circuits, there are several key criteria which need to be optimized with respect to each other in order to create a design and an on-chip layout for an integrated circuit which provides the best overall results within certain cost and other design constraints. Such criteria include the size of the chip, power consumption of the chip and the speed of operation for the various functions accomplished within the chip. This kind of optimization analysis is normally done on a workstation or other computer system running various analysis and design programs which, in turn, operate to weigh the relative significance of the various design criteria for each specific application in which the designed integrated circuit will be implemented.
One of the most important of these design criteria is the time delay involved in a particular design for a digital signal to travel through a particular path or paths on the integrated circuit to get to certain key points or nodes of the circuit in the minimum time possible consistent with performance requirements. Ideally, the best design of an integrated circuit is the design that enables a signal to traverse a predetermined layout between certain key points in the smallest amount of time, wherein the layout or integrated circuit consumes minimal power and requires the smallest amount of semiconductor area to implement. In most cases, these criteria are mutually conflicting so that one cannot be improved without decreasing the efficacy of another at least to some extent.
For example, in the "sizing" of particular transistors for a proposed integrated circuit design, it is noted that although increasing the area of the transistors in the design will, in general, decrease the time delay in signal transmission, it will also increase the size and power of the chip, and therefore limit the applicability of the chip in certain product areas, as well as reduce the profitability of the chip. Also, a decrease in the size of a chip will, in general, decrease its power consumption, heat generation and chip signal interference. The priority of each of the above design constraints and others, and the best possible solution for a particular application, will depend upon the application in which the integrated circuit is to be used. In most cases, the best result is obtained through a combination of trade-offs which is optimized with specific regard to, and consideration of, the specific application for the integrated circuit being designed.
In order to determine the level of optimization and evaluate the effectiveness of any particular design, certain analyses have been used in the industry. One such general evaluation technique is timing analysis which is intended to estimate the time delay of a signal through a digital circuit as described above. In the past, many such timing approaches have been used by circuit designers in order to optimize the efficacy or "strength" or size of a new combination of criteria values for a new integrated circuit design. One such approach adopted by some in the past is the method by which first, a timing analysis is made for a circuit, then a "critical path" is identified and only the components or elements on that critical path are analyzed for possible sizing optimization. While that approach is generally satisfactory, there is a need for an improved method for a more comprehensive approach to the sizing optimization of elements in an integrated circuit design.
In addition to the optimization of signal transition speed and silicon area for integrated circuits being designed, there is also a continuing need to optimize the design process itself which provides the optimized netlist, such that the desired circuit netlist and circuit optimizations can be accurately obtained more quickly and efficiently during the chip design process. That requirement can also be met through the implementation of the approaches and methods hereinafter disclosed.